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POWER MANAGEMENT Description
Semtechs SC1544, SC243x and SC1112A or SC1114 provide all the voltages necessary for an ACPI system. The SC1544 offers five independant supplies: a 5V dual supply for USB, a 3.3V dual supply for PCI, a 3.3V or 2.5V dual supply for memory, a 1.5V or 3.3V supply for AGP and a 1.8V supply. The AGP supply is programmble using the system TYPEDET signal. An on-board internal charge pump eliminates the need for P-channel MOS.ETs and enables function from a single 5V supply (system 5VSB). All dual outputs are over current protected. The SC1544 differs from the SC1547 in three important ways: 1) the device initially starts up in S5, and not G0 like the SC1547; 2) the gate drives for the 1.8V and AGP outputs are always high in normal operation; 3) no OCP on the 1.8V and AGP outputs.
ACPI Controller for Advanced Motherboards
PRELIMINARY .eatures
K Complete programmable supply for instantly available K Supports 2.5V memory or 3.3V memory (-2.5 or -3.3 K 5V dual and 3.3V dual supplies are programmable to K Integrated AGP voltage supply with TYPEDET signal K K K K K
for 3.3V or 1.5V operation Integrated LDO for 1.8V supply Integrated charge pump removes the need for PMOS .ETs, enables single supply operation Over current protection on all dual outputs Inherent soft-start capability TSSOP-24 package be active or inactive in S5 option in part number) PC systems
SC1544
Applications
K Instantly available motherboards
Typical Application Circuit
5V GND 3.3V GND 5VSB GND 5V DUAL GND 3.3V DUAL GND 3.3V DUAL MEM GND AGP GND 1.8V GND C8 100uF/6.3V C7 100uF/6.3V Q8 IRLR3103 C6 100uF/6.3V Q7 IRLR3103 C5 100uF/6.3V Q5 IRLR3103 Q6 IRLR3103 C4 100uF/6.3V Q3 IRLR3103 C3 100uF/6.3V C2 100uF/6.3V C1 100uF/6.3V
Q1 IRLR3103
Q2 IRLR3103
Q4 IRLR3103
U1 1 2 3 4 5 G5 3.3VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI
SC1544-3.3 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13 C9 0.01uF C10 0.1uF C11 1uF
TYPEDET PWR_OK EN /SLP_S3 /SLP_S5 USB PCI
6 7 8 9 10 11 12
Revision 3, May 2002
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SC1544
POWER MANAGEMENT Absolute Maximum Ratings
Parameter Input Supply Voltage Logic Input Pins Charge Pump Output Voltage Thermal Impedance Junction to Case Thermal Resistance Junction to Ambient Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. V FC J C J A TA TJ TSTG TLEAD Symbol V 5V S B Maximum -0.6 to 7 -0.6 to V5VSB -0.6 to 13.2 15.6 83.8 0 to 70 0 to 125 -65 to +150 300
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Units V V V C/W C/W C C C C
Electrical Characteristics(1)
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25C. Values in bold apply over full operating ambient temperature range.
Parameter IN Supply Voltage Quiescent Current
Symbol
Test Conditions
Min
Typ
Max
Units
V 5V S B IQ All states (S0, S3, S5, disabled)
4.5
5.0 10
5.5 15 20
V mA
Undervoltage Lockout Threshold Voltage VUVLO V5VSB Rising 3.5 4.0 4.4 V
Logic Inputs (EN, PCI, PWR_OK, /S3, /S5, TYPEDET, USB) Logic Pin Sink Current(2) Logic Pin Source Current ISINK ISOURCE VBIAS = 5V, all logic pins EN, VEN = 0V PCI, TYPEDET, USB, VPIN = 0V /S3, PWR_OK, VPIN = 0V /S5, V/S5 = 0V Threshold Voltage VIH VIL 1.8V Output Output Voltage(3) V1.8V 1mA IOUT 720mA 1.764 1.746
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0.1 0.5 50 100 150 2.4
1 3 200 400 600
A A
V 0.8 V
1.800
1.836 1.854
V
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SC1544
POWER MANAGEMENT Electrical Characteristics (Cont.)(1)
Parameter 1.8V Output (Cont.) Line Regulation(3) Load Regulation(3) Gate 8 Drive Voltage(4) REGLINE REGLOAD VG8(HI) VG8(LO) Gate 8 Drive Current(4) IG8(SOURCE) IG8(SINK) Sense Pin Bias Current I1.8V V5VSB = 4.75V to 5.25V, IOUT = 0A V5VSB = 5V, IOUT = 0A to 720mA V1.8V = 1.7V, IG8 = 10A S3, IG8 = -10A V1.8V = 1.7V, VG8 = 5V V1.8V = 1.9V, VG8 = 3V Sinking, V1.8V = 1.8V 2 -3.5 -70 8.00 0.01 0.01 8.75 0.8 4 -5 -100 -130 A 1.0 mA 0.10 0.20 % % V Symbol Test Conditions Min Typ
PRELIMINARY
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25C. Values in bold apply over full operating ambient temperature range.
Max
Units
2.5V/3.3V Dual Memory Output Output Voltage(5) V3.3VDM 1mA IOUT 720mA -1.5 -2.5 Line Regulation(5) Load Regulation(5) Gate 5 Drive Voltage(6) REGLINE REGLOAD VG5(HI) VG5(LO) Gate 5 Drive Current(6) IG5(SOURCE) IG5(SINK) Gate 6 Drive Voltage(7) VG6(HI) VG6(LO) Gate 6 Drive Current(7) IG6(SOURCE) IG6(SINK) Sense Pin Bias Current I3.3VDM V5VSB = 4.75V to 5.25V, IOUT = 0A V5VSB = 5V, IOUT = 0A to 720mA V3.3VDM = VOUT(NOM) - 100mV, IG5 = 10A, S0 IG5 = -10A, S3 V3.3VDM = VOUT(NOM) - 100mV, VG5 = 5V, S0 V3.3VDM = VOUT(NOM) + 100mV, VG5 = 3V, S0 V3.3VDM = VOUT(NOM) - 100mV, IG6 = 10A, S3 IG6 = -10A, S0 V3.3VDM = VOUT(NOM) - 100mV, VG6 = 5V, S3 V3.3VDM = VOUT(NOM) + 100mV, VG6 = 3V, S3 Sinking, 3.3V option, V3.3VDM = 3.3V Sinking, 2.5V option, V3.3VDM = 2.5V 3.3V Dual Output Output Voltage(8) V3.3VD 1mA IOUT 720mA 3.250 3.217 Line Regulation(8) Load Regulation(8) REGLINE REGLOAD V5VSB = 4.75V to 5.25V, IOUT = 0A V5VSB = 5V, IOUT = 0A to 720mA 0.01 0.01 3.300 3.350 3.383 0.10 0.20 % % V 2 -3.5 -330 -215 2 -3.5 8.00 8.00 0.01 0.01 8.75 0.8 4 -5 8.75 0.8 4 -5 -475 -310 -620 -405 A 1.0 mA V 1.0 mA VOUT(NOM) +1.5 +2.5 0.10 0.20 % % V %
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SC1544
POWER MANAGEMENT Electrical Characteristics (Cont.)(1)
Parameter 3.3V Dual Output (Cont.) Gate 3 Drive Voltage(9) VG3(HI) VG3(LO) Gate 3 Drive Current(9) IG3(SOURCE) IG3(SINK) Gate 4 Drive Voltage(10) VG4(HI) VG4(LO) Gate 4 Drive Current(10) IG4(SOURCE) IG4(SINK) Sense Pin Bias Current 5V Dual Output Gate 2 Drive Voltage(11) VG2(HI) VG2(LO) Gate 2 Drive Current(11) IG2(SOURCE) IG2(SINK) Gate 1 Drive Voltage(12) VG1(HI) VG1(LO) Gate 1 Drive Current(12) IG1(SOURCE) IG1(SINK) Sense Pin Bias Current(2) AGP Output Output Voltage(13) VAGP 1mA IOUT 720mA -2.0 -3.0 Line Regulation(13) Load Regulation(13) Gate 7 Drive Voltage(4) REGLINE REGLOAD VG7(HI) VG7(LO) V5VSB = 4.75V to 5.25V, IOUT = 0A V5VSB = 5V, IOUT = 0A to 720mA VAGP = VOUT(NOM) - 100mV, IG7 = 10A VAGP = VOUT(NOM) + 100mV, IG7 = -10A 8.00 0.01 0.01 8.75 0.8 1.0 VOUT(NOM) +2.0 +3.0 0.10 0.20 % % V V % I5VD IG2 = 10A IG2 = -10A VG2 = 5V VG2 = 3V IG1 = 10A IG1 = -10A VG1 = 5V VG1 = 3V V 5V D = 5 V 0.5 -10 0.5 -10 8.00 8.00 8.75 40 0.7 -14 8.75 40 0.7 -14 16 A 100 V mV mA 100 V mV mA I3.3VD IG3 = 10A IG3 = -10A VG3 = 5V VG3 = 3V V3.3VD = 3.2V, IG4 = 10A V3.3VD = 3.4V, IG4 = -10A V3.3VD = VOUT(NOM) - 100mV, VG4 = 5V V3.3VD = VOUT(NOM) + 100mV, VG4 = 3V Sinking, V3.3VD = 3.3V 2 -3.5 -70 0.5 -10 8.00 8.00 8.75 40 0.7 -14 8.75 0.8 4 5 -100 -130 A 1.0 mA V 100 V mV mA Symbol Test Conditions Min Typ
PRELIMINARY
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25C. Values in bold apply over full operating ambient temperature range.
Max
Units
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SC1544
POWER MANAGEMENT Electrical Characteristics (Cont.)(1)
Parameter AGP Output (Cont.) Gate 7 Drive Current(4) IG7(SOURCE) IG7(SINK) Sense Pin Bias Current IAGP VAGP = VOUT(NOM) - 100mV, VG7 = 5V VAGP = VOUT(NOM) + 100mV, VG7 = 3V VAGP = 3.3V, TYPEDET = High VAGP = 1.5V, TYPEDET = Low FC (Charge Pump) Output Voltage Overcurrent Protection(14) Trip Threshold Short Circuit Immunity(15) VTH(OC) 30 1 50 70 75 %VOUT ms V FC V 5V S B = 5 V 9.0 9.5 10.0 V 2 -3.5 -235 -70 4 -5 -340 -105 -445 -140 A mA Symbol Test Conditions Min Typ
PRELIMINARY
Unless specified: all applicable silver box supplies (3.3V, 5V, 5VSB) 5%, GND = 0V, VSENSE PINS = VOUT(NOM), TA = 25C. Values in bold apply over full operating ambient temperature range.
Max
Units
Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Guaranteed by design. (3) Applies to S0 only. (4) Gates 7 and 8 are high whenever 5VSB is present and greater than VUVLO, unless the over current protection has been tripped. (5) Applies to S3 sleep state only for 3.3V Dual Memory option. Applies to both S0 and S3 sleep state for 2.5V Dual Memory Option (6) Gate 5 is high in S0 and low in the S3 and S5 sleep states. (7) Gate 6 is high in the S3 sleep state and low in S0 and in the S5 sleep state. (8) Applies to S3 sleep state and S5 sleep state when the PCI pin is high. (9) Gate 3 is high in S0 and low in the S3 and S5 sleep states. (10) Gate 4 is high in the S3 sleep state and the S5 sleep state when the PCI pin is high. Gate 4 is low in S0, and in the S5 sleep state when the PCI pin is low. (11) Gate 2 is high in S0 and low in the S3 and S5 sleep states. (12) Gate 1 is high in the S3 sleep state and the S5 sleep state when the USB pin is high. Gate 1 is low in S0, and in the S5 sleep state when the USB pin is low. (13) Applies to S0 only. VAGP = 3.3V when TYPEDET is high and 1.5V when the TYPEDET pin is low. (14) Applies to 2.5V/3.3V Dual Memory, 3.3V Dual and 5V Dual outputs when enabled only. When an output is disabled, that output is not monitored for OCP. The 1.8V and AGP outputs do not have over current protection. (15) Minimum and maximum time limits for over current protection to trip when powered up (or enabled) into a shorted output and when a short is applied to an enabled, OCP protected output.
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SC1544
POWER MANAGEMENT State Diagram Showing Gate Drive Status PRELIMINARY
Note: (1) State machine will not allow illegal transitions such as S3 to S5. In order to get to S5 from S3, it is first necessary to enter S0.
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SC1544
POWER MANAGEMENT Timing Diagrams
Startup
PRELIMINARY
Normal Operation
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SC1544
POWER MANAGEMENT Power Matrix
This table shows which output is powered from which supply under each system state.
System USB State S0 S3 S5 X(1) X(1) 0 0 1 1 PCI /S3 X(1) X(1) 0 1 0 1 1 0 0 0 0 0 /S5 1 1 0 0 0 0 PWR_OK 1 0 0 0 0 0 3.3V/2.5V Dual Memory 3.3V 5V S B OFF OFF OFF OFF 3.3V D u al 3.3V 5V D u al 5V 3.3V/1.5V AGP(2) 3.3V ON ON ON ON ON 1.8V(2) 3.3V ON ON ON ON ON All outputs off PCI enabled USB enabled PCI & USB enabled Comments
PRELIMINARY
5V S B 5V S B OFF 5V S B OFF OFF OFF 5V S B
5V S B 5V S B
Notes: (1) X = dont care. In S0 and S3, the 3.3V dual and 5V dual outputs are not affected by the state of the PCI and USB pins. These outputs are only controlled by the sate of the PCI and USB pins in S5. (2) Gate 7 and Gate 8 are high in all states with 5VSB > UVLO and OCP not tripped. If powered from 3.3V as shown in the table, the AGP and 1.8V outputs are only present in S0, and will ramp with the 3.3V supply as it comes up. This avoids dips in the 3.3V supply which would otherwise occur if Gate 7 and Gate 8 went high after the 3.3V supply came up, demanding high currents to charge output capacitors. If powered from 5VSB they can be used to create 1.5VSB, 1.8VSB or 3.3VSB as required.
Gates At A Glance
This table shows which gate drive pin controls which MOS.ET:
Gate Number: 1 2 3 4 5 6 7 8 Pin Number: 18 19(1) 19(1) 22 1 3 4 24 5V S B 5V 3.3V 5V S B and 3.3V 5V S B 3.3V 3.3V 3.3V/2.5V Dual Memory 3.3V/2.5V Dual Memory AGP 1.8V pass device/linear regulator(2) linear regulator linear regulator linear regulator Drives the FET betw een: 5V Dual 5V Dual 3.3V Dual 3.3V Dual FET mode: pass device pass device pass device linear regulator
Notes: (1) Note common pin for Gate 2 and Gate 3 - both .ETs are operating as pass devices only in S0. (2) .ET is acting as a pass device for 3.3V Dual Memory and as a linear regulator for 2.5V Dual Memory.
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SC1544
POWER MANAGEMENT Pin Configuration
Top View
PRELIMINARY Ordering Information
Part Number SC1544TS-X.XTR (1)(2) SC1544EVB(3) P ackag e TSSOP-24 N/A
Notes: (1) Where -X.X denotes voltage options. Available voltages are: 2.5V and 3.3V (2.5V Dual Memory or 3.3V Dual Memory). (2) Only available in tape and reel packaging. A reel contains 2500 devices. (3) Evaluation board for SC1544 - specify voltage option when ordering. TSSOP-24
Block Diagram
Marking Information
Top View
x.x = voltage option (Example: 3.3) yyww = Date code (Example: 0012 xxxxxx = Lot number (Example: P94A01)
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SC1544
POWER MANAGEMENT Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name G5 3.3VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PC I -CAP +CAP FC 5V S B 5V D G1 G2/3 GND 3.3VD G4 1.8V G8 Pin Function Gate drive for MOSFET between VCC3 and 2.5V/3.3V Dual Memory. Sense pin for 3.3V Dual Memory. Sense pin for 2.5V Dual Memory for 2.5V option. Gate drive for MOSFET between 5VSB and 2.5V/3.3V Dual Memory. Gate drive for MOSFET between VCC3 and 1.5V/3.3V AGP. High when 5VSB is present and greater than UVLO. Sense pin for 1.5V/3.3V AGP. Select 1.5V or 3.3V for AGP, high = 3.3V. Power_OK signal from silver box. Enable signal active high. Connect to 5VSB if not being used. Cycling the enable pin will reset the over current latches. Pulling this pin low (with /S5 high) causes the device to enter the S3 sleep state. Pulling both /S3 and /S5 low will cause the device to enter the S5 sleep state. Pulling this pin low along with /S3 causes the device to enter the S5 sleep state. Enable pin for 5V Dual during S5 sleep state, high = ON. Enable pin for 3.3V Dual during S5 sleep state, high = ON. Negative end of charge pump capacitor. Connect a 10nF ceramic capacitor between this pin and pin 14 (+CAP). Positive end of charge pump capacitor. Charge pump output (9V nominal). Decouple this pin with a 0.1F ceramic capacitor. 5V standby supply from silver box. Decouple this pin with a 1F ceramic capacitor. Sense pin for 5V Dual. Gate drive for MOSFET between 5VSB and 5V Dual. Gate drive for MOSFETs between VCC5 and 5V Dual and VCC3 and 3.3V Dual. Reference ground. Sense pin for 3.3V Dual. Gate drive for MOSFET between 5VSB and 3.3V Dual. Sense pin for 1.8V LDO. Gate drive for MOSFET between VCC3 (or 5VSB) and 1.8V. High when 5VSB is present and greater than UVLO.
PRELIMINARY
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SC1544
POWER MANAGEMENT Typical Applications Circuits
5V GND 3.3V GND 5VSB GND 5V DUAL GND 3.3V DUAL GND 3.3V DUAL MEM GND AGP GND 1.8V GND C8 100uF/6.3V U1 1 2 3 4 5 TYPEDET PWR_OK EN /SLP_S3 /SLP_S5 USB PCI 6 7 8 9 10 11 12 G5 3.3VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI SC1544-3.3 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13 C9 0.01uF C10 0.1uF C11 1uF C7 100uF/6.3V Q8 IRLR3103 C6 100uF/6.3V Q7 IRLR3103 C5 100uF/6.3V Q5 IRLR3103 Q6 IRLR3103 C4 100uF/6.3V Q3 IRLR3103 Q4 IRLR3103 C3 100uF/6.3V Q1 IRLR3103 Q2 IRLR3103 C2 100uF/6.3V C1 100uF/6.3V
PRELIMINARY
Notes: (1) 3.3V option shown - see below for Q5 configuration for 2.5V option. (2) 1.8V output shown powered from 3.3V. If powered from 5VSB, this becomes 1.8VSB. (3) See Applications Information.
3.3V GND 5VSB GND 2.5V DUAL MEM GND C6 100uF/6.3V 1 2 3 Q5 body diode in series with D1 to pre-charge 2.5V Dual Memory D1 to ensure that the linear regulator will still regulate 4 5 6 7 8 9 10 11 12 C3 100uF/6.3V Q5 Q6 U1 G5 2.5VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI SC1544-2.5 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13 C2 100uF/6.3V D1
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SC1544
POWER MANAGEMENT Applications Information
Theory Of Operation The SC1544 provides a simple way to power five seperate voltage buses while controlling them correctly using the ACPI control interface (PWR_OK, /SLP_S3 and /SLP_S5). It requires only a single supply rail (5VSB from the system silver box) to operate. An internal charge pump generates the gate voltages required to enable the use of n-channel .ETs throughout the design. The external .ETs are operated in two discrete modes: 1) as pass devices where VOUT = VIN - (IOUT * RDS(ON)) 2) as linear regulators. Please refer to the Gates At A Glance section on page 8 and the Typical Applications Circuits on page 11 to determine which .ETs operate in which mode. Linear Mode: the SC1544 contains a bandgap reference trimmed for optimal temperature coefficient which is fed into the inverting input of an error amplifier. The output voltage of each linear regulator (monitored by the sense pin for that output) is divided down internally using a resistor divider and compared to the bandgap voltage. The error amplifier drives the gate of the appropriate external .ET to maintain the voltage at the non inverting input, and hence the output voltage. Pass Device Mode: when a particular output is enabled (please refer to the Power Matrix section on page 8) in pass mode (i.e. 5VSB to 5V Dual), the appropriate gate drive will be driven high to turn the .ET hard on, minimizing the voltage drop due to IOUT*RDS(ON). The sense pins serve two functions: 1) to sense the output voltage for the linear regulators 2) to sense the output voltage for over current protection Over Current Protection is provided for all dual outputs. OCP is implemented by utilizing the RDS(ON) of the .ETs. As the output current increases, the regulation loop maintains the output voltage (linear mode only) by turning on the .ET more and more. Eventually, as the RDS(ON) low limit is reached (pass devices are already operating at this point) the .ET will be unable to turn on any further and the output voltage will start to fall. When the output voltage falls to approximately 50% of nominal, all outputs are latched off. Toggling the enable pin or cycling 5VSB will reset the latch.
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PRELIMINARY
To prevent false latching due to capacitor inrush currents, low supply rails or momentary overloads, the current limit latch has a timer. If VOUT is above the OCP threshold (VTH(OC)) before the timer times out, then the outputs do not latch. Reducing Commutation Noise The slew rate of the linears is slow enough to provide soft commutation. The non-linear switch outputs (5V and 3.3V Duals) have fast slew rates. It may be necessary to put a resistor in series with the gate to reduce transients (3.3V Dual Memory shown):
3.3V
R1 1 Q5 IRLR3103 10k (typ.) 2 3 4 3.3V DUAL MEM 5 6 7 8 9 10 11 12
U1 G5 3.3VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI
SC1544-3.3 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13
Another possible source of commutation noise occurs at startup on 3.3V Dual Memory, when the standby .ET, Q6 and the pass-through .ET, Q5 are both off. 3.3V Dual Memory will charge to 3.3V minus 0.7V (the drop across the Q5 body diode). When PWR_OK asserts, Q6 turns on shorting 3.3V to 3.3V Dual Memory, pulling it down locally momentarily. This should not be an issue as long as there is sufficient capacitance on 3.3V locally. Another way to reduce this drop is to place a schottky diode across Q5 with the cathode towards 3.3V Dual Memory so this rail charges to 3.3V minus 0.4V, thus reducing the drop when Q5 turns on:
3.3V
C1 Increase bulk capacitance (preferred)
+ Q5 IRLR3103
TO PIN 1
D1 (optional) TO PIN 2
3.3V DUAL MEM
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SC1544
POWER MANAGEMENT Applications Information (Cont.)
Linear Regulator Stability When extremely low ESR capacitors (Oscons, Polymers, high value ceramics) are used on outputs requiring fast transients (3.3V/2.5V memory), the linear regulators may exhibit some overshoot and/or transient instability. External compensation may be necessary (5VSB to 3.3V Dual Memory shown):
U1 3.3V DUAL MEM R1 1k 2 C1 22nF Q6 IRLR3103 3 4 5 6 5VSB 7 8 9 10 11 12 1 G5 3.3VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI SC1544-3.3 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13
PRELIMINARY
.or the 2.5V Dual Memory linear regulator:
R2 2.5 350A * 100 71
2.5V < VOUT (AJUSTED) < 3.3V
GND
C6 100uF/6.3V
R1
I SENSE U1 1 2 G5 2.5VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI SC1544-2.5 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13
VOUT (FIXED) 3 R2 4 5 6 7 8 9 10 11 12
Another possibility is to use dual capacitor types for the load capacitor - a ceramic capacitor will provide high frequency decoupling for the load while an electrolytic capacitor (high ESR) will tame the Q to prevent instability:
3.3V DUAL MEM
The output voltage can only be adjusted upwards from the fixed output voltage, and can be calculated using the following equation:
R1 VOUT( ADJUSTED ) = VOUT(FIXED ) * 1 + + R1 * ISENSE Volts R2
C1 Electrolytic - bulk
+
C2 Ceramic - high frequency decoupling
Adjusting the Output Voltage of the Linear Regulators It is possible to adjust the output voltage of the linear regulators (1.8V, 2.5V Dual Memory and AGP) by applying an external resistor divider to the sense pin (see below). Since the sense pins sink a nominal 100A (1.8V LDO, 150A for the 1.5V AGP LDO, 325A for the 3.3V AGP LDO and 350A for the 2.5V Dual Memory LDO), the resistor values should be selected to allow 100x that current to flow through the divider. This will ensure that variations in the sense current will have negligible affect on the output voltage regulation. Thus a target value for R2 (maximum) can be calculated:
R2 VOUT(FIXED ) ISENSE * 100
Therefore to set the 2.5V Dual Memory linear regulator to 2.6V, for example, R1 = 2.8 and R2 = 69.8. The maximum voltage to which an output can be set using this method is limited by the input voltage to the .ET(s) and the RDS(ON) of the .ET(s). Please note that this technique cannot be used for the 3.3V Dual Memory, 3.3V Dual and 5V Dual outputs since the output is switched via a pass device (i.e. not regulated) when not in S0. .ault Protection Hints Loss of AC Power: if it is possible during brownouts or momentary loss of AC power to the computer silver box that PWR_OK can assert low while S3 and S5 remain high then the over current protection may trigger. This is because the state machine will ignore this illegal transition and monitor all outputs as if they are still in S0, despite the fact that the inputs are going away. If 5VSB decays slowly, S3 and S5 remain high, and one output drops below the OCP threshold for long enough
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SC1544
POWER MANAGEMENT Applications Information (Cont.)
.ault Protection Hints (Cont.) that the OCP times out then the outputs will latch off. Then if the AC power returns after the OCP latches off, but before the 5VSB supply drops below UVLO, then the device will not start up again until EN or 5VSB is cycled. One way to avoid this happening is to force the device into S3 if PWR_OK goes low but S3 and S5 remain high using the circuit shown below. This will supply the outputs from 5VSB which will either cause 5VSB to drop below UVLO and reset the part when the AC power comes back up, or it may prevent OCP occuring at all. Either way correct functionality will be guaranteed once AC power returns.
U1 1 2 3 4 5 6 PWR_OK D1 1N4148 /SLP_S3 R1 4.7k 11 12 7 8 9 10 G5 2.5VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI SC1544-2.5 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13
PRELIMINARY
Incorrect Signals .rom Silver Box: Some silver boxes have been found that produce incorrect voltages on the PWR_OK line, producing dangerous negative voltage spikes up to -1V or greater. Such spikes exceed the absolute maximum ratings for this device and can cause the device to malfunction. If a supply produces such spikes they can be clamped to GND using a small schottky diode as shown below, completely removing any threat.
U1 1 2 3 4 5 6 PWR_OK 7 8 D1 9 10 11 12 G5 2.5VDM G6 G7 AGP TYPEDET PWR_OK EN /S3 /S5 USB PCI SC1544-2.5 G8 1.8V G4 3.3VD GND G2/3 G1 5VD 5VSB FC +CAP -CAP 24 23 22 21 20 19 18 17 16 15 14 13
2002 Semtech Corp.
14
www.semtech.com
SC1544
POWER MANAGEMENT Outline Drawing - TSSOP-24 PRELIMINARY
Land Pattern - TSSOP-24
Contact Information
Semtech Corporation Power Management Products Division 200 .lynn Road, Camarillo, CA 93012 Phone: (805)498-2111 .AX (805)498-3804
2002 Semtech Corp. 15 www.semtech.com

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